The present invention is related to charge transfer circuits of the type comprising first and second capacitors and a charge transfer transistor for transferring a plurality of discrete charge packets from the first to the second capacitor. Charge transfer circuits of the foregoing type are particularly useful in monolithic analog to digital converters such as those described in U.S. Patent Application Ser. No. 628,542, filed Nov. 3, 1975, and assigned to the assignee of the present application. Exemplary of several other applications of such circuits in U.S. Pat. No. 3,819,954, which discloses a charge transfer delay line circuit.
While the uses of charge transfer circuits are varied, a common requirement of charge transfer analog to digital converters is that an equal amount of charge be transferred from the first to the second capacitor during each charge transfer operation. In applications of this type, a signal proportional to the analog voltage being converted is applied to the second capacitor. During each of the plurality of charge transfer operations, a metered charge packet, having a constant magnitude, is transferred to the second capacitor. Since the magnitude of each metered charge packet is ideally constant, the number of charge packets required to change the voltage across the second capacitor from the first proportional to the analog voltage to be converted to second predetermined value is ideally proportional to the magnitude of the analog signal being converted.
The foregoing relationship is modified in actual application by two variables: (1) a thermally induced leakage current in the semi-conductor substrate in which the first and second capacitors and the charge transfer transistor are preferably formed; and (2) the threshold voltage of the transistor. Various circuits have been proposed to compensate for variations in the thermally induced leakage current which would normally modify the size of the charge packets. The present application is directed towards an apparatus for preventing any variations in the size of the charge packet due to variations in the threshold voltage of the charge transfer transistor.
When a MOSFET is operated in a "shelf" mode, its source is isolated, and when the transistor turns on, charge flows from its source to its drain until the voltage at its source becomes equal to its gate voltage less its threshold voltage. This feature of a MOSFET transistor makes it suitable for use as a charge transfer transistor for transferring a discrete packet of charge from a first capacitor located at its source to a second capacitor located at its drain. Particularly, each time the MOSFET is biased into the "shelf" mode, a discrete packet of charge .DELTA.Q is transferred from the first to the second capacitor in accordance with the following formula: EQU .DELTA.Q = C(V.sub.g - V.sub.t - V.sub.c) (1)
wherein C is the capacitance of the first capacitor, V.sub.g is the gate voltage of the transistor, V.sub.t is the threshold voltage of the transistor and V.sub.c is the voltage across the first capacitor at the initiation of the charge transfer operation. It is apparent from equation (1) that any changes in the threshold voltage V.sub.t will result in variations in the size of the metered charge packet transferred from the first to the second capacitor.
The magnitude of the threshold voltage V.sub.t of a MOSFET can vary both as a function of the temperature of the MOSFET and of the magnitude of the drain voltage. Accordingly, if these parameters are not properly taken into account, the magnitude of the threshold voltage, and therefore the magnitude of the charge packets, can vary during each use of the charge transfer circuit. Such a result is clearly undesirable since it would degrade the presumed linear relationship between the magnitude of the analog voltage being converted and the number of charge packets required to change the charge across the second capacitor from the first value representative of the analog voltage and the second predetermined value.